1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices and, more particularly, to a method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor (such transistor combination being hereinafter sometimes referred to as Bi-CMOS transistor) such as to preclude deterioration and improve the characteristics of the bipolar transistor.
2. Description of the Related Art
Bi-CMOS LSI, which has the merits of the high density integration capacity and low power consumption of the CMOS transistor and high speed operation of the bipolar transistor, is attracting attention in view of recent demands for further LSI scale increase and performance improvement. In the process of manufacturing the Bi-CMOS LSI, however, the inter-element isolation technique has problems as will be described.
In the process, the oxide film thickness can not be made excessively large in order to reduce conversion difference due to the commonly termed bird's beak generated at the time of LOCOS. For example, in a CMOS process with a gate length condition of 0.3 to 0.5 .mu.m, the oxide film thickness is 0.25 to 0.4 .mu.m.
Meanwhile, in the bipolar transistor it is necessary to separate an epitaxial layer usually of the order of 1.0 m with a LOCOS oxide film or with a LOCOS oxide film and a p-n junction. This means that the oxide film thickness is 0.8 to 1.0 .mu.m.
The inventor has earlier proposed to solve this problem by etching semiconductor layer portion around the bipolar transistor (as disclosed in Japanese Patent Application No. 35110/91). The proposed technique will now be described with reference to FIGS. 1-A to 1-G.
(a) In the first place, a Psub &lt;100&gt; substrate 10 is prepared, and a buried layer 1 is formed in a bipolar transistor region of the substrate by Sb diffusion or like well-known method.
Then, an n-epitaxial layer 2 with .rho. of 1.0 .OMEGA..multidot.cm and t of 1.0 .mu.m is formed with epitaxial techniques.
Then, substrate Si is etched with usual dry etching techniques. This etching permits sufficient inter-element isolation to be obtained even when the LOCOS film thickness is small. In the process, the substrate is etched by about 400 nm by taper etching using a blend gas composed of SiCl4 and N2 (see FIG. 1-A).
(b) Then, an inter-element isolation insulating film 11 is formed with usual LOCOS techniques. At this time, the LOCOS oxide film thickness is set to about 400 nm. Setting the oxide film thickness to be excessive leads to increase of the inter-element isolation region due to commonly termed bird's beak or generation of substrate Si crystal defects due to stress generated at the time of selective oxidization. In a subsequent step, a collector electrode 7 is formed in a collector electrode region of the bipolar transistor by ion implanting P+ using a resist mask (see FIG. 1-B).
Further, a p+-type region 4 is formed in the isolation region by ion implanting B+ through the LOCOS oxide film.
(c) Then, oxidization is carried out; for instance steam oxidization is carried out at 350.degree. C. for about 15 minutes, thus forming an oxide film 12 having a thickness of about 15 nm.
Then, poly Si 21 of about 50 nm is formed over the entire surface by a reduced pressure CVD process.
Then, a resist is formed to cover the entire surface, and its portion on the base electrode region of the bipolar transistor is selectively etched away.
Then with this patterned resist as a mask, the poly Si oxide layer is etched by RIE.
This etching is carried out in two steps, comprising a first step of etching poly Si with SF6/C2Cl2F3 gas and a second step of etching SiO2 with O2/CHF3 gas (see FIG. 1-C).
(d) Then, a second poly Si layer 22 of about 50 nm is formed by the reduced pressure CVD, and then a high-melting metal marterial, e.g., WSix 23, with a thickness of about 100 nm, is formed by the CVD process.
Then, a resist is formed and patterned such as to cover a base electrode region.
With this patterned resist as a mask, the WSix, second poly Si layer and first poly Si layer are then etched by RIE. This etching is done by using SF6/C2Cl3F3 gas.
Then, an insulator, e.g., SiO2 24, is formed to a thickness of about 300 nm by the CVD process. (FIG. 1-D).
(e) Then, a resist is formed over the entire surface, and its portion on an emitter/base formation region of the bipolar transistor is etched away. With this patterned resist as a mask, the SiO2, WSix and poly Si in the emitter/base formation region are etched away. The etched part is designated at 20.
The etching is done in two steps, i.e., a first step of etching SiO2 with O2/CHF3 gas and a second step of etching WSix and poly Si with SF6/C2Cl3F3 gas.
In the second step of etching, sufficient selection ratio can be taken for SiO2. Thus, SiO2 22 can remain on the emitter/base formation region, and no etching damage is caused (FIG. 1-E).
(f) Then, a link base region is formed by ion implanting BF2.
Then, a SiO2 spacer 25 is formed by carrying out CVD and RIE of SiO2 continuously. For example, a side wall width of 0.2 to 0.3 m can be obtained under the conditions of SiO2 CVD to 500 nm and RIE overetching of 10%, thus realizing an emitter/base contact width of a quarter .mu.m.
Subsequently, an emitter poly Si layer 26 of about 100 nm is formed by the reduced CVD process.
Then, emitter/base is formed by B+ ion implantation, As+ ion implantation and then a heat treatment. Then, the poly Si is etched away while leaving the emitter electrode region (FIG. 1-F).
(g) Then, an insulator, e.g., SiO2 27 is formed to a thickness of about 300 nm by the CVD process.
Then the SiO2 layer 27 on emitter/base/collector contact is etched away using a resist mask. Then, a metal lead 28 of Ti/TiN/Al-Si or polypoly Si/W silicide is formed on the entire surface and patterned with a regist mask, thus forming electrodes 3E, 3B and 3C. Thus, a bipolar transistor is completed (FIG. 1-G).
In the above example, the depth of diffusion in the formation of a high impurity concentration layer for the collector electrode may be made less than that in the prior art by removing the semiconductor layer in the collector electrode region.
However, as shown in FIG. 1-B, the ion implantation process for the formation of the high impurity concentration layer for the collector electrode is still necessary, which is undesired in view of the process step reduction.
Further, the ion implantation step requires high dose ion implantation usually of the order of 10.sup.15 cm-2 in terms of the dose, thus posing the problem that separation of the resist after the ion implantation is very difficult.
Further, the process of manufacturing Bi-CMOS has problems which will now be discussed by showing the process.
FIGS. 2-A to 2-H are fragmentary sectional views showing an upper portion of part of a silicon substrate including a bipolar transistor region and a channel PMOS transistor region in the process of manufacturing a Bi-CMOS transistor by the prior art method.
In the prior art method, as shown in FIG. 2-A, an n---type layer 31 is formed in the a bipolar transistor collector region and also in a PMOS transistor region, a p-type isolation 32 in a region of isolating the individual devices of the bipolar transistor and the CMOS transistor, a p---type layer 33 in a biplar transistor base region, and a p+--type layer 34, a field oxide film 35 and an oxide film 37' in a PMOS transistor source/drain region. Then, poly Si is formed over the entire surface of the Si substrate 30 by the reduced pressure CVD process. Then, the poly Si is removed by RIE such as to leave poly Si in a CMOS transistor gate electrode region.
Then, an oxide film is formed over the entire surface of the Si substrate by the reduced pressure CVD process, and it is then entirely etched back by RIE. As a result, a side wall oxide film 38 is formed on the side wall surfaces of poly Si 36a in the CMOS transistor gate electrode region, as shown in FIG. 2-B.
Then, a p+--type layer 34 is formed by implanting P ions in the p-channel MO8 transistor source/drain region.
Then, as shown in FIG. 2-C, an oxide film 37 is formed by thermal oxidization, and then a BPSG film 39 is formed by the normal pressure CVD process.
Then, as shown in FIG. 2-D, contact holes are formed by RIE in portions corresponding to bipolar transistor base, emitter and collector electrode formation regions. Then, as shown in FIG. 2-B, poly Si 36 is formed over the entire Si substrate surface by the reduced pressure CVD process. Then, as shown in FIG. 2-F, other poly Si 36 than poly Si 3c in the base, emitter and collector electrode regions is etched away by RIE.
Then, as shown in FIG. 2-G, contact holes are formed by RIE in the CMOS transistor source and drain electrode regions. Then, as shown in FIG. 2-H, Al is deposited and then selectively etched away by RIE such as to leave it on the electrode regions of the bipolar transistor and the CMOS transistor. Thus, a base, an emitter and a collector electrode 30B, 30E and 30C and also a source and a drain electrode 39S and 30D are formed.
In the above prior art method, however, in the step of obtaining the structure shown in FIG. 2-E by RIE etching back the oxide film 37' shown in FIG. 2-A formed by the CVD process over the entire Si substrate surface, the Si substrate surface is also etched in the active region 31a of the bipolar transistor. In addition, in the step of RIE forming the contact holes in portions corresponding to the bipolar transistor base, emitter and collector electrode regions as shown in FIG. 2-D, the Si substrate surface is etched in the individual electrode regions. In this way, in the prior art process even the Si substrate surface active region which is not desired to be etched is etched, thus resulting in the bipolar transistor characteristic deterioration.
To solve the above problem of the etching damage, it may be thought to use wet etching in lieu of RIE in the step shown in FIG. 2-D. In this case, however, fine processing can not be obtained due to the character of isotropic etching carried out as the wet etching.
Further, in the prior art process the emitter and base electrodes are formed such that they are separated from each other. This means a transistor size increase, thus leading to the parasitic capacitance increase and integration density reduction, which is undesired from the standpoints of various characteristics.